4.5.3

Configuration 3

•

Delayed: SLOT0 data MSB is sampled on the second rising edge of BCLK after rising edge of WCLK

(delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one)

•

Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal

to zero)

delayed

Note:

Setup and hold times are defined in Table 5. TDM interface characteristics.

4.5.4

Configuration 4

•

Delayed: SLOT0 data MSB is sampled on the second falling edge of BCLK after rising edge of WCLK

(delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one)

•

Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5

equal to one)

delayed

Note:

Setup and hold times are defined in Table 5. TDM interface characteristics.

4.6

TDM clocks and MCLK requirements

The relationship between TDM clocks and MCLK should be:

•

Both BCLK and WCLK must be obtained from MCLK by integer division. This requirement is mandatory

since ADC is clocked by MCLK, so the TDM data rate must be perfectly synchronous in frequency and

phase with the decimated ADC data rate.

•

The BCLK/WCLK ratio must be an integer value.

AIS25BA

TDM clocks and MCLK requirements

DS14019 - Rev 1

page 13/31