LQFP100 datasheet(31/204 Pages) STMICROELECTRONICS

31 / 204 page

DS8626 Rev 9

31/203

STM32F405xx, STM32F407xx

Description

Standby mode, the SRAM and register contents are lost except for registers in the

backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,

a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event

occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed

and the V12 domain is controlled by an external power.

2.2.20

VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external

supercapacitor, or from VDD when no external battery and an external supercapacitor are

present.

VBAT operation is activated when VDD is not present.

The VBAT pin supplies the RTC, the backup registers and the backup SRAM.

Note:

When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events

do not exit it from VBAT operation.

When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no

more available and VBAT pin should be connected to VDD.

2.2.21

Timers and watchdogs

The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight

general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

Timer

type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Complemen-

tary output

Max

interface

clock

(MHz)

Max

timer

clock

(MHz)

Advanced

-control

TIM1,

TIM8

16-bit

Up,

Down,

Up/down

Any integer

between 1

and 65536

Yes

168

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