DI25 datasheet(19/416 Pages) MICROCHIP

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DS30010118D-page 19

PIC24FJ256GA705 FAMILY

FIGURE 1-1:

PIC24FJ256GA705 FAMILY GENERAL BLOCK DIAGRAM

Instruction

Decode and

Control

PCH

Program Counter

16-Bit ALU

Data Bus

Inst Register

Divide

Support

Inst Latch

EA MUX

Interrupt

Controller

EDS and

Stack

Control

Logic

Repeat

Control

Logic

Data Latch

Data RAM

Address

Latch

Address Latch

Extended Data

Data Latch

Address Bus

Literal

Control Signals

16 x 16

W Reg Array

Multiplier

17x17

OSCI/CLKI

OSCO/CLKO

VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

HLVD &

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulators

Voltage

VCAP

PORTA(1)

PORTC(1)

(12 I/Os)

(8 I/Os)

PORTB

(16 I/Os)

Note 1:

Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-3 for specific implementations by pin count.

BOR functionality is provided when the on-board voltage regulator is enabled.

Some peripheral I/Os are only accessible through remappable pins.

Comparators(3)

Timer2/3(3)

Timer1

RTCC

A/D

12-Bit

OC/PWM

SPI

I2C1-2

EPMP/PSP

1-3(3)

IOCs(1)

UART

REFO

1-3(3)

1-2(3)

1-3(3)

CTMU

Space

Program Memory/

CLC1-2(1)

DMA

Controller

Data

DMA

Data Bus

Table Data

Access Control

MCCP1/2/3

PCL

BOR(2)

Read AGU

Write AGU

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