SH79F024XU datasheet(76/92 Pages) SINOWEALTH

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SH79F

SH79F082

082

8.8

8 Power

Power

Power Management

Management

8.8

8.1

.1 Feature

Feature

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Two power saving modes: Idle mode and Power-Down mode

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Two ways to exit Idle and Power-Down mode: interrupt and reset

To reduce power consumption, SH79F082 supplies two power saving modes: Idle mode and Power-Down mode. These two

modes are controlled by PCON & SUSLO register.

8.8.2

8.8.2 IIIIdle

dle

dle M

Mode

ode

In this mode, the clock to CPU is frozen, the program execution is halted, and the CPU will stop at a defined state. But the

peripherals continue to be clocked. When entering idle mode, all the CPU status before entering will be preserved. Such as:

PSW, PC, SFR & RAM are all retained.

By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the IDL bit in PCON

register, will make SH79F082 enter Idle mode. If the consecutive instruction sequence requirement is not met, the CPU will

clear either SUSLO register or IDL bit in the next machine cycle. And the CPU will not enter Idle mode. The setting of IDL bit

will be the last instruction that CPU executed.

There are two ways to exit Idle mode:

(1) An interrupt generated. After warm-up time, the clock to the CPU will be restored, and the hardware will clear SUSLO

register and IDL bit in PCON register. Then the program will execute the interrupt service routine first, and then jumps to

the instruction immediately following the instruction that activated Idle mode.

(2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the

CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH79F082 will be

reset. And the program will execute from address 0000H. The RAM will keep unchanged and the SFR value might be

changed according to different function module.

8.8.3

8.8.3 Power-Down

Power-Down

Power-Down M

Mode

ode

The Power-Down mode places the SH79F082 in a very low power state. Power-Down mode will stop all the clocks including

CPU and peripherals. If WDT is enabled, WDT block will keep on working. When entering Power-Down mode, all the CPU

status before entering will be preserved. Such as: PSW, PC, SFR & RAM are all retained.

By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the PD bit in PCON

CPU will clear either SUSLO register or PD bit in the next machine cycle. And the CPU will not enter Power-Down mode.

The setting of PD bit will be the last instruction that CPU executed.

Note:

Note: If IDL bit and PD bit are set simultaneously, the SH79F082 enters Power-Down mode. The CPU will not go in Idle

mode when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode.

There are two ways to exit the Power-Down mode:

(1) An active external Interrupt such as INT0, INT1 & INT4 will make SH79F082 exit Power-Down mode. The oscillator will

start after interrupt happens, after warm-up time, the clocks to the CPU and peripheral will be restored, the SUSLO

routine. After completion of the interrupt service routine, program execution resumes with the instruction immediately

following the instruction that activated Power-Down mode.

(2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled). This will restore the clock to

the CPU after warm-up time, the SUSLO register and the PD bit in PCON register will be cleared by hardware, finally the

SH79F082 will be reset. And the program will execute from address 0000H. The RAM will keep unchanged and the SFR

value might be changed according to different function module.

Note:

Note: In order to entering Idle/Power-Down, it is necessary to add 3 NOPs after setting IDL/PD bit in PCON.

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