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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH79F024XU 데이터시트(PDF) 14 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU 데이터시트(HTML) 14 Page - SINOWEALTH Electronic Ltd |
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14 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 14 7.1.2 7.1.2 7.1.2 7.1.2 Enhanced Enhanced Enhanced Enhanced C C C CPU PU PU PU C C C Core ore ore ore SFRs SFRs SFRs SFRs � Extended 'MUL' and 'DIV' instructions: 16bit*8bit, 16bit/8bit � Dual Data Pointer � Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH79F082 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the register is applied to hold the upper part of the operand/result. The AUXC register is used during 16 bit operand multiply and divide operations. For other instructions it can be treated as another scratch pad register. After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard 8051 instructions. To enable the 16 bit mode operation, the corresponding enable bit in the INSCON register must be set. Dual Dual Dual Dual Data Data Data Data Pointer Pointer Pointer Pointer Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data pointer is called DPTR1. DPTR1 is the same with DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers. The DPS bit in INSTCON register is used to choose the active pointer. The user can switch data pointers by toggling the DPS bit. And all DPTR-related instructions will use the currently selected data pointer. Register Register Register Register Table Table Table Table 7 7 7 7....2 2 2 2 Data Pointer Select Register Note Note Note Note:::: BKS[1:0] should set as 00,because it only has one bank. Operation Operation Operation Operation Result Result Result Result A A A A B B B B AUXC AUXC AUXC AUXC MUL MUL MUL MUL INSCON.2 = 0; 8 bit mode (A)*(B) Low Byte High Byte --- INSCON.2 = 1; 16 bit mode (AUXC A)*(B) Low Byte Middle Byte High Byte DIV DIV DIV DIV INSCON.3 = 0; 8 bit mode (A)/(B) Quotient Low Byte Remainder --- INSCON.3 = 1; 16 bit mode (AUXC A)/(B) Quotient Low Byte Remainder Quotient High Byte 86H 86H 86H 86H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 INSCON INSCON INSCON INSCON BKS1 BKS0 - - DIV MUL - DPS R/W R/W R/W R/W R/W R/W - - R/W R/W - R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 - - 0 0 - 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-6 7-6 7-6 7-6 BKS[1:0] BKS[1:0] BKS[1:0] BKS[1:0] SFR SFR SFR SFR B B B Bank ank ank ank S S S Selection election election election Bit Bit Bit Bit 00: SFR Bank selected others: Reserved 3 3 3 3 DIV DIV DIV DIV 16 16 16 16 bit/8 bit/8 bit/8 bit/8 bit bit bit bit Divide Divide Divide Divide Selection Selection Selection Selection Bit Bit Bit Bit 0: 8 bit Divide 1: 16 bit Divide 2 2 2 2 MUL MUL MUL MUL 16 16 16 16 bit/8 bit/8 bit/8 bit/8 bit bit bit bit Multiply Multiply Multiply Multiply Selection Selection Selection Selection Bit Bit Bit Bit 0: 8 bit Multiply 1: 16 bit Multiply 0 0 0 0 DPS DPS DPS DPS Data Data Data Data Pointer Pointer Pointer Pointer Selection Selection Selection Selection Bit Bit Bit Bit 0: Data pointer 1: Data pointer1 |
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