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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH79F166AP/044PR 데이터시트(PDF) 18 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR 데이터시트(HTML) 18 Page - SINOWEALTH Electronic Ltd |
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18 / 113 page  SH79F166A 18 7. Normal Function 7.1 CPU 7.1.1 CPU Core SFR Feature CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Stack Pointer (SP) The Stack Pointer Register is 8 bits wide, It is incremented before data is stored during PUSH, CALL executions and it is decremented after data is out of stack during POP, RET, RETI executions. The stack may reside anywhere in on-chip internal RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at location 08H. Program Status Word Register (PSW) The PSW register contains program status information. Table 7.1 PSW Register D0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PSW CY AC F0 RS1 RS0 OV F1 P R/W R/W R/W R/W R/W R/W R/W R/W R Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 CY Carry flag bit 0: no carry or borrow in an arithmetic or logic operation 1: a carry or borrow in an arithmetic or logic operation 6 AC Auxiliary Carry flag bit 0: an auxiliary carry or borrow in an arithmetic or logic operation 1: an auxiliary carry or borrow in an arithmetic or logic operation 5 F0 F0 flag bit Available to the user for general purposes 4-3 RS[1:0] R0-R7 Register bank select bits 00: Bank0 (Address to 00H-07H) 01: Bank1 (Address to 08H-0FH) 10: Bank2 (Address to 10H-17H) 11: Bank3 (Address to 18H-1FH) 2 OV Overflow flag bit 0: no overflow happen 1: an overflow happen 1 F1 F1 flag bit Available to the user for general purposes 0 P Parity flag bit 0: an even number of “one” bits in the Accumulator 1: an odd number of “one” bits in the Accumulator Data Pointer Register (DPTR) DPTR consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers. |
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