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SH79F166AP/044PR 데이터시트(PDF) 74 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR 데이터시트(HTML) 74 Page - SINOWEALTH Electronic Ltd |
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74 / 113 page ![]() SH79F166A 74 Programming Note: (1) Set PWMLO register to 55H and select the PWM module system clock. (2) Set the PWM period/duty cycle by writing proper value to the PWM period control register (PWMP) or PWM duty control register (PWMD). First set the low Byte, then the high Byte. (3) Select the PWM output mode of the duty cycle by writing the PWM0S bit in the PWM control register (PWMC). (4) In order to output the desired PWM waveform, enable the PWM module by writing “1” to the EPWM bit in the PWM control register (PWMC). (5) If the PWM period cycle or duty cycle is to be changed, the writing flow should be followed as described in step b or step c. Then the revised data are loaded into the re-load counter and the PWM module starts counting at next period. (6) Change the data in PWMLO register not equal to 55h in order to enhance the anti-noise ability. PWMn clock t PWM 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 01 02 03 04 05 06 07 08 Write [PPn.11, PPn.0] = 0DH Write [PDn.11, PDn.0] = 07H PWMn output (PWMnS = 0) Period cycle = 0FH x t PWM Duty cycle = 06H x t PWM Period cycle = 0DH x t PWM Duty cycle = 06H x t PWM Duty cycle = 07H x t PWM n = 0 or 1 PWM output Period or Duty cycle changing example 8.3.5 PWM01 Generally, PWM01 have a 180∘phase delay with PWM0 as shown below when there is no dead time inserted. It is automatically generated by hardware when EPWM01 in PWM timer enable register is set. PWM0 output (PWM0S = 0) PWM01 output (PWM0S = 0) Note: (1) That even if PWM0 are not enabled, PWM01 can also work if enabled. (2) If EFLT is set, When a valid event occurs on FLT pin, PWM01 and PWM0 are both LOW (PWMS = 0)or both HIGH (PWMS = 1). |
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