8

Application notes

8.1

Output voltage divider

The error amplifier reference voltage is 0.85 V typical.

Referring to Figure 23 for Type II compensator and Figure 25 for type III, the output voltage is adjusted as follows:

VOUT=0.8∙ 1+RURD

(25)

Figure 28. L3751 application schematic

CIN

SS/TRK

RT

SW

ILIM

RILIM

BST

HO

LO

PGND

LF

COUT

VCC

VIN

RRT

COMP

FB

AGND

CSS

RF

CF

CP

RD

RS

CS

RU

FB

VOUT

VIN

EN

SYNCOUT

SYNCIN

CVCC

CBST

D

QHS

QLS

8.2

Synchronization (forced PWM)

Beating frequency noise is an issue when multiple switching regulators populate the same application board. The

L3751 synchronization circuitry features the same switching frequency for a set of regulators simply connecting

the SYNCOUT of the master to the SYNCIN pin of the slaves together, so preventing beating noise. The master

device provides the synchronization signal to the others.

For proper synchronization of multiple regulators, all of them have to be configured with the same switching

frequency (see Section 5.2), so the same resistor value connected at the RT pin. Alternatively, the SINCIN can be

driven by an external clock signal in accordance with electrical parameters defined in Table 7. The external clock

frequency range at SYNCIN pin is -20% to +50% of the programmed oscillator frequency with the RT resistor.

L3751

Application notes

DS13841 - Rev 1

page 27/41