L3751 datasheet(3/41 Pages) STMICROELECTRONICS

3 / 41 page

Pin configuration

Figure 2. QFN pin connection (top view)

SS/TRK

COMP

AGND

SYNCOUT

SYNCIN

BST

VCC

PGND

Table 1. Pin description

QFN Pin

Die PAD

Name

Function

EN/UVLO

The central tap of a resistor divider connected to this pin helps to design the

enable and undervoltage lockout thresholds referred to the input voltage.

•

VEN/UVLO < 0.4 typ.: the device is in shutdown mode

•

0.4 V typ. < VEN/UVLO < 1.2 V typ.: device in standby - VCC regulator

active - SS/TRK pin in low impedance

•

VEN/UVLO > 1.2 V typ.: SS/TRK pin released and the device ready to start

- 10 µA current flows to the external resistor divider to design the enable

hysteresis.

A pull-down resistor to AGND programs the oscillator frequency (100 kHz – 1

MHz) and adjust the internal ramp for constant PWM gain.

SS/TRK

The pin circuitry features a current generator (10 μA typ.) to charge an external

capacitor and so program the soft-start time, otherwise it implements voltage

tracking if connected to an auxiliary voltage source. In soft-start phase, the

SS/TRK voltage is the error amplifier reference and then the internal reference

becomes active after the startup phase has ended. The pin is clamped 115

mV above the FB voltage for controlled recovery from an overcurrent event or

clamped to ground during stand-by operation or internal fault.

COMP

Output of the internal error amplifier. Connect the compensation network

between COMP and the FB.

Inverting input of the internal error amplifier. Connect the compensation network

between COMP and the FB.

AGND

Analog ground

L3751

Pin configuration

DS13841 - Rev 1

page 3/41

L3751 데이터시트(PDF) 3 Page - STMicroelectronics

L3751 데이터시트(HTML) 3 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

데이터시트 다운로드

링크 URL