L9963T datasheet(12/45 Pages) STMICROELECTRONICS

12 / 45 page

The internal pull-down guarantees a limp home operation in low frequency in case of pin-loss.

Figure 6. ISOFREQ pin structure

3.2.1.5

BNE/CPOL

BNE/CPOL is a digital input/output pin whose configuration depends on the value of NSLAVE latched during

Trimming & Config Latch:

•

When NSLAVE = 0 (Slave configuration), this pin acts as BNE (Buffer Not Empty) digital output and its

purpose is to implement interrupt based communication with the MCU. When asserted high, it means that

the RX queue stores at least one frame.

•

When NSLAVE = 1 (Master configuration), this pin acts as digital input for the selection of CPOL (Clock

POLarity):

–

CPOL = 0 (shorted to GND) implies that the clock inactive level (when NCS is high) is low.

–

CPOL = 1 (shorted to VDD) implies that the clock inactive level (when NCS is high) is high.

The internal pull-down is always enabled during Trimming & Config Latch and in Normal state.

The BNE output buffer is disabled if NSLAVE = 1 has been latched during Trimming & Config Latch. The CPOL

input buffer is permanently enabled.

In case NSLAVE = 0 has been latched during Trimming & Config Latch, BNE output buffer is kept enabled

while in Normal state. A short to GND/VDD detection is implemented to protect the BNE output buffer. If the

value forced on the BNE output buffer differs from the one sampled by the CPOL input buffer for more than

TBNE_SHORT_DET, the BNE output buffer is put into HiZ. Automatic re-engagement of the BNE output buffer occurs

upon next wakeup sequence (MCU needs to toggle DIS pin).

L9963T

Pin configuration

DS13590 - Rev 4

page 12/45

L9963T 데이터시트(PDF) 12 Page - STMicroelectronics