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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VL6180 데이터시트(PDF) 44 Page - STMicroelectronics |
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VL6180 데이터시트(HTML) 44 Page - STMicroelectronics |
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44 / 73 page  Device registers VL6180 44/73 DocID024986 Rev 14 6.2.7 IDENTIFICATION__DATE_LO Address: 0x007 Type: R/W Reset: 0xYY, register default overwritten at boot-up by NVM contents. Description: Part of the register set that can be used to uniquely identify a module. 6.2.8 IDENTIFICATION__TIME Address: 0x008:0x009 Type: R/W Reset: 0xYYYY, register default overwritten at boot-up by NVM contents. Description: Part of the register set that can be used to uniquely identify a module. 7 654 321 0 identification__day identification__phase R/W R/W [7:3] identification__day: Manufacturing day (bits[4:0]). [2:0] identification__phase: Manufacturing phase identification (bits[2:0]). 15 14 13 12 11 10 9876543210 identification__time R/W [15:0] identification__time: Time since midnight (in seconds) = register_value * 2. |
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