L99MOD50XP datasheet(25/42 Pages) STMICROELECTRONICS

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DS12615 Rev 4

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L99MOD50XP

Functional description of the SPI

4.1

General description

Standard ST-SPI Interface Version 3.0.

The SPI communication is based on a Serial Peripheral Interface structure using CSN (Chip

Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial Clock) signal

lines.

4.1.1

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) is in high impedance state. A low signal wakes up the device and a serial

communication can be started. The state when CSN is going low until the rising edge of

CSN is called a communication frame.

Note:

The device includes a test mode. This mode is activated by a dedicated sequence which

includes a high voltage at the CSN pin. The CSN pin must be kept at nominal voltage levels

in order to avoid accidental activation of the test mode.

4.1.2

Serial Data In (DI)

The input pin is used to transfer data serially into the device. The data applied to the DI is

sampled at the rising edge of the CLK signal.

4.1.3

Serial Clock (CLK)

This input signal provides the timing of the serial interface. The Data Input (DI) is latched at

the rising edge of Serial Clock CLK. The SPI can be driven by a micro controller with its SPI

peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial Data Out

(DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock CLK must be

active only during a frame (CSN low). Any other switching of CLK close to any CSN edge

could generate set up/hold violations in the SPI logic of the device.

The clock monitor counts the number of clock pulses during a communication frame (while

CSN is low). If the number of CLK pulses does not correspond to the frame width indicated

in the <SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in

the <Global Status Byte> is set.

Note:

Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

4.1.4

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high

impedance to a low or high level depending on the global status bit 7 (Global Error Flag).

The first rising edge of the CLK input after a high to low transition of the CSN pin transfers

the content of the selected status register into the data out shift register. Each subsequent

falling edge of the CLK shifts the next bit out.

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