VD6283TX datasheet(11/59 Pages) STMICROELECTRONICS

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3.4.2

I2C new device address

The VD6283 provides a feature to assign a new I2C device address which should be used by the system

implementer. The dedicated procedure below needs to be followed to re-program the device address.

The device should be in the OFF state (i.e. powered off) for more than 1 ms.

The host drives the GPIO1 signal to low state (i.e. GND level).

Then, the system powers up the VD6283.

After power up time has elapsed (tpu = 0.03 ms) , the host can send a valid I2C command with the desired

new device address.

Finally, wait until the host can release the GPIO1 signal (i.e. the host output should be set in high

impedance).

The VD6283 I2C address is now changed and should be used as a reference address to communicate with the

VD6283.

Note:

Once the VD6283 address is changed, any incoming I2C transactions with the default address (0x40) will be

ignored by the VD6283.

Note:

If the host attempts to change the VD6283 I2C address after the first I2C transaction is received, the device will

ignore such a request.

Note:

The new I2C device address procedure should be repeated at each VD6283 power up.

Note:

During the VD6283 power up phase, it is recommended to suspend any I2C transactions to avoid unwanted I2C

device address assignment.

Note:

The external pull up resistor on GPIO1 is required to avoid unintended I2C device address assignment. Please

refer to the recommended application schematics.

3.4.3

I2C interface timing characteristics

Timing characteristics are shown in the tables below. Please refer to the figure below for parameters details.

Table 7. I2C interface - timing characteristics for Fast mode plus (1 MHz)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

FI2C

Operating frequency

—

1000

kHz

tLOW

Clock pulse width low

0.5

—

µs

tHIGH

Clock pulse width high

0.26

—

tSP

Pulse width of spikes which are

suppressed by the input filter

—

tBUF

Bus free time between transmissions

0.5

—

µs

tHD.STA

Start hold time

0.26

—

tSU.STA

Start set-up time

0.26

—

tHD.DAT

Data in hold time

—

0.9

tSU.DAT

Data in set-up time

—

SCL/SDA rise time

—

120

SCL/SDA fall time

—

120

tSU.STO

Stop set-up time

0.26

—

µs

tVD.DAT

Data valid time

—

0.4

Ci/o

Input/output capacitance (SDA)

—

Cin

Input capacitance (SCL)

—

Load capacitance

—

140

550

VD6283TX

I2C interface

DS13735 - Rev 1

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