| 전자부품 데이터시트 검색엔진 |
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STW81101 데이터시트(PDF) 20 Page - STMicroelectronics |
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STW81101 데이터시트(HTML) 20 Page - STMicroelectronics |
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20 / 42 page ![]() General description STW81101 20/42 The SERCAL bit should be set to "1" at each division ratio change. It should be noted that in order to reset the autocalibrator State Machine after a power-up, and anyway before the first calibration, the INITCAL bit should be set to "1" and back to "0" (this operation is automatically performed by the Power On Reset circuitry). The calibration takes approximately 7 periods of the PFD Frequency. The maximum allowed fPFD to perform the calibration process is 1 MHz. Using an higher FPFD the following procedure should be adopted: 1. Calibrate the VCO at the desired frequency with an fPFD less than 1 MHz 2. Set the A, B and R dividers ratio for the desired fPFD VCO Voltage Amplitude Control The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level expected on the resonator nodes. Table 8. Voltage level expected on the resonator nodes Code A[1:0] Differential output voltage (Vp) 00 1.1 01 1.3 10 1.9 11 2.1 |
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