MEC1632 datasheet(79/636 Pages) MICROCHIP

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DS00001592B-page 79

MEC1632

6.0

HOST INTERFACE

6.1

General Description

6.1.1

OVERVIEW

The host processor communicates with the MEC1632 via the LPC Bus Interface. The host processor communicates

through a series of read/write registers in the MEC1632. Register access is accomplished through programmed I/O

cycles. All I/O transfer cycles are 8 bits wide.

The Logical Devices physically located in the MEC1632 are identified in Table 4-2, “Host Logical Devices in the

MEC1632,” on page 59 and Table 5-1, “Logical Devices,” on page 63. The base addresses of logical devices with reg-

isters located in LPC I/O space, including the Keyboard Controller, can be moved via the configuration registers located

in the LPC Interface Configuration Register Space.

All configuration register access for the MEC1632 are accessed indirectly through the LPC I/O Configuration Register

Port (IOCR-Port.) The default I/O address is 2Eh and 2Fh, but the IOCR-Port can be relocated by either the host or the

EC. The relocation value can be stored in the BAR Init Register so that the updated IOCR-Port address is used when

the main power rail cycles. Detailed description of the MEC1632 Configuration Space is in Section 5.0, "Logical Device

Configuration," on page 63.

All LPC transactions that are claimed by the MEC1632 are mapped by the LPC interface to an address in the

MEC1632’s AHB address space. All these addresses can also be accessed by the Embedded Controller in the

MEC1632.

TABLE 6-1:

TARGETS OF LBC CYCLES CLAIMED BY THE MEC1632

Target

Acronym

Description

LPC Type

LPC IO Configuration Register Port

IOCR-Port

Standard LPC 2Eh/2Fh Port which per-

mits BIOS access. This port can be

relocated by the ARC.

I/O

Logical Devices

Targets physically located in the

MEC1632.

The Keyboard Controller Interface

uses a Port at 60h/64h

I/O

Configuration Register

256 byte space per Logical Device

accessed by BIOS through the IOCR-

Port.

I/O through CR-

Port

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