DGD0215/0216

Document number: DS40183 Rev. 6 - 2

9 of 11

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June 2022

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DGD0215/0216

PCB Layout Information

The DGD0215 and DGD0216 High Speed, Low-Side, single Gate Drivers demand a fast switching current through VCC, and in the power

switching circuit a much larger current will be switched through the MOSFET. Typical applications are PFC or boost converter. Particular

consideration for layout is key to ensuring optimal operation of the Gate Driver IC as well as to minimizing ringing and noise on the power line

(VBUS) and ground. Figure 20 shows an example layout of the DGD0216 in the Low-Side power switching of a PFC circuit. Figure 21 shows the

schematic of the layout shown in Figure 20, followed by a description of layout considerations for the DGD0215 and DGD0216.

Figure 20. Example Layout of DGD0216 Driving a Low-Side MOSFET (For Example PFC Circuit)

Figure 21. Schematic for Layout Example Circuit Shown in Figure 20

In Gate Driver circuits, most of the current occurs during turning on/off, so when designing optimal layout, it is best to consider the charge transfer

during turn on/off.

When the DGD0216 turns on, charge will flow from C1/C2 through the logic circuits in the Gate Driver IC and directly to GND. But the majority of

the charge will flow from C1/C2 via the internal P-channel MOSFET (see Functional Block Diagram Output Stage), through the OUT pin to charge

the Gate of the MOSFET, Q1; the return is from the Source of Q1 through the current sense resistors (R2 and R3) and to GND (back to C1/C2).

Hence this loop must be as short as possible to minimize stray inductance. C1 should be a low ESR ceramic capacitor and along with gate

resistor (R1) and MOSFET (Q1) should be located close to the DGD0216 to minimize the inductance of that loop. When the device turns off, the

charge on the MOSFET Gate sinks current into the IC through the internal N-channel MOSFET to GND.