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TC35679FSG 데이터시트(PDF) 18 Page - Toshiba Semiconductor |
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TC35679FSG 데이터시트(HTML) 18 Page - Toshiba Semiconductor |
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18 / 45 page ![]() TC35679FSG-002 2018-01-17 18 4.3.5. UART Baud Rate Setting TC35679 UART interface has a programmable baud rate setting function. The UART baud rate is generated from 26 MHz clock, and can be set according to the following equation depending on over sampling number and dividing ratio. Ratio Dividing Number Sampling Over Frequency Clock Generating Rate Baud BaudRate UART × = Table 4-2 shows examples of UART Baud rate settings. If other target baud rates are required, please contact our engineering department. Table 4-2 UART Baud rate settings Target baud rate [bps] Actual baud rate [bps] Over sampling rate Frequency dividing ratio 9600 9587.021 12 226 14400 14396.46 14 129 19200 19174.04 12 113 28800 28856.83 17 53 38400 38461.54 13 52 57600 57777.78 15 30 76800 76923.08 13 26 115200 115555.6 15 15 153600 153846.15 13 13 230400 232142.9 16 7 307200 305882.4 17 5 460800 464285.7 14 4 921600 928571.4 14 2 Note: Error of target baud rate and the actual baud rate is to be set to within 1 %. 4.3.6. TX message spacing function TC35679 spaces more than 12 time frames between different TX messages making less than 12 time frames between TX frames in a TX message when several TX frames belong to one TX message. Host CPU is able to know the boundaries between TX messages by measuring time frames between TX frames. Figure 4-8 TX frames and TX messages UART TX data UART TX massage UART TX message < 12 time frames < 12 time frames < 12 time frames > 12 time frames 1 time frame |
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