TC3567CFSG-002

2018-04-06

13

3.

System Configuration

3.1. Block Diagram

Figure 3-1 shows block diagram of TC3567C.

TC3567C is powered by single voltage between 1.9 V and 3.6 V.

The chip has built-in DCDC and LDO requiring external capacitors. It uses 26 MHz reference clock and 32.768 kHz sleep clock.

External memory interface is SPI or I2C, and host CPU interface is UART.

Figure 3-1 Example of TC3567C system configuration

RF Block

26MHz

X’tal

ClockGen/

Clock

Management

RF PLL

Power　

Management

Controller

VBAT

1.9 to

3.6V

Baseband

Block

UART

2ch

HOST

I/F

SPI/

I2C

PWM

4ch

GPIO

ADC

6ch

Modem

ARM®

　

Cortex®-M0

Mask

ROM

RAM

(BackUp)

Selector

Ref

VBAT

32kHz

X’tal

DCDC

LDO

Level

Detector

Flash

ROM

VDDCORE2