STA335BWSQS datasheet(36/70 Pages) STMICROELECTRONICS

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STA335BWSQS

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6.6

Configuration register F (addr 0x05)

6.6.1

Output configuration

Note:

To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

OCFG1

OCFG0

110

Table 43.

OCFG

Bit

RST

Name

Description

0RW

OCFG0

Selects the output configuration

1RW

OCFG1

Table 44.

Output configuration engine selection

OCFG[1:0]

Output configuration

Config pin

2 channel (full-bridge) power, 2 channel data-out:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

LineOut1

→ 3A/3B

LineOut2

→ 4A/4B

Line Out Configuration determined by LOC register

2 (half-bridge), 1 (full-bridge) on-board power:

→ 1A, Binary 0 °

→ 1B, Binary 90°

3A/3B

→ 2A/2B, Binary 45°

1A/B

→ 3A/B, Binary 0°

2A/B

→ 4A/B, Binary 90°

2 channel (full-bridge) power, 1 channel DDX:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

3A/3B

→ 3A/3B

EAPDEXT and TWARNEXT Active

1 channel mono-parallel:

→ 1A/1B, w/ C3BO 45°

→ 2A/2B, w/ C3BO 45°

1A/1B

→ 3A/3B

2A/2B

→ 4A/4B

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