STM32H753II datasheet(25/361 Pages) STMICROELECTRONICS

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DS12117 Rev 8

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STM32H753xI

Functional overview

3.3.3

Embedded SRAM

All devices feature:

•

512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.

•

SRAM1 mapped on D2 domain: 128 Kbytes

•

SRAM2 mapped on D2 domain: 128 Kbytes

•

SRAM3 mapped on D2 domain: 32 Kbytes

•

SRAM4 mapped on D3 domain: 64 Kbytes

•

4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses,

and is retained in Standby or VBAT mode.

•

RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed

either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave

of the CPU(AHBP):

–

64 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical

real-times routines by the CPU.

–

128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service

routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for

load/store operations) thanks to the Cortex®-M7 dual issue capability.

The MDMA can be used to load code or data in ITCM or DTCM RAMs.

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in

memories may occur. They can be detected and corrected by ECC. This is an expected

behavior that has to be managed at final-application software level in order to ensure data

integrity through ECC algorithms implementation.

SRAM data are protected by ECC:

•

7 ECC bits are added per 32-bit word.

•

8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algorithm. It supports single-error correction

and double-error detection.

3.4

Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option

bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF

which includes:

•

All Flash address space

•

All RAM address space: ITCM, DTCM RAMs and SRAMs

•

The System memory bootloader

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