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STM32H753II 데이터시트(PDF) 38 Page - STMicroelectronics

부품명 STM32H753II
상세설명  32-bit Arm® Cortex®-M7 480MHz MCUs, 2MB Flash,1MB RAM, 46 com. and analog interfaces, crypto
PDF  361 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32H753II 데이터시트(HTML) 38 Page - STMicroelectronics

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Functional overview
STM32H753xI
38/360
DS12117 Rev 8
short circuit detector to detect saturated analog input values (bottom and top range):
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
storage of minimum and maximum values of final conversion data
refreshed by software
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
“regular” or “injected” conversions:
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
“injected” conversions for precise timing and with high conversion priority
3.24
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
Table 4. DFSDM implementation
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X



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