MPC8540 datasheet(220/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-6

Freescale Semiconductor

Core Complex Overview

— Signal processing engine APU (SPE APU). Note that the SPE is not a separate unit; SPE

computational and logical instructions are executed in the simple and multiple-cycle

units used by all other computational and logical instructions, and 64-bit loads and

stores are executed in the common LSU. Figure 5-1 shows how execution logic for

SU1, the MU, and the LSU is replicated to support operations on the upper halves of the

GPRs.

The e500 register set is modified as follows:

– GPRs are widened to 64 bits to support 64-bit load, store, and merge operations. Note

that the upper 32 bits are affected only by 64-bit instructions.

– A 64-bit accumulator (ACC) has been added.

– The signal processing and embedded floating-point status and control register

(SPEFSCR) provides interrupt control and status for SPE and embedded

floating-point instructions.

These registers are shown in Figure 5-6. SPE instructions are grouped as follows:

– Single-cycle integer add and subtract with the same latencies for SPE APU

operations as for the 32-bit equivalent

– Single-cycle logical operations

– Single-cycle shift and rotate

– Four-cycle integer pipelined multiplies

– 4-, 11-, 19-, and 35-cycle integer divides

– If rA or rB is zero, a floating-point divide takes 4 cycles. All other cases take 29

cycles.

– 4-cycle SIMD pipelined multiply-accumulate (MAC)

– 64-bit accumulator for no-stall MAC operations

– 64-bit loads and stores

– 64-bit merge instructions

•

Cache structure—Separate 32-Kbyte, 32-byte line, 8-way set-associative level 1 instruction

and data caches

— 1.5-cycle cache array access, 3-cycle load-to-use latency

— Pseudo-LRU (PLRU) replacement algorithm

— Copy-back data cache that can function as a write-through cache on a page-by-page

basis

— Supports all Book E memory coherency modes

— Supports EIS-defined cache-locking instructions, as listed in Table 5-3

•

Dual-issue superscalar control

— Two-instructions-per-clock peak issue rate

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