MPC8540 datasheet(217/1302 Pages) FREESCALE

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Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

5-3

Book E allows processors to provide auxiliary processing units (APUs), which are extensions to

the architecture that can perform computational or system management functions. One of these on

the e500 is the signal processing engine APU (SPE APU), which includes a suite of vector

instructions that use the upper and lower halves of the GPRs as a single two-element operand.

Most APUs implemented on the e500 are defined by the Freescale Semiconductor Book E

implementation standards (EIS).

5.1.1

Upward Compatibility

The e500 provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits, and

two-element 64-bit data types for the embedded vector floating-point APU which provides scalar

and vector single-precision instructions that operate on operands comprised of two 32-bit elements

and the SPE APU, which provides an extensive instruction set for 64-bit vector integer and

fractional operations.

The embedded scalar floating-point APU provides 32-bit single-precision instructions.

NOTE

The SPE APU and embedded floating-point APU functionality is

implemented in all PowerQUICC III devices. However, these

instructions will not be supported in devices subsequent to

PowerQUICC III. Freescale Semiconductor strongly recommends

that use of these instructions be confined to libraries and device

drivers. Customer software that uses SPE or embedded floating-point

APU instructions at the assembly level or that uses SPE intrinsics will

require rewriting for upward compatibility with next-generation

PowerQUICC devices.

Freescale Semiconductor offers a libmoto_e500 library that uses SPE

and embedded floating-point APU instructions. Freescale will also

provide libraries to support next-generation PowerQUICC devices.

5.1.2

Core Complex Summary

The core complex is a superscalar processor that can issue two instructions and complete two

instructions per clock cycle. Instructions complete in order, but can execute out of order. Execution

results are available to subsequent instructions through the rename buffers, but those results are

recorded into architected registers in program order, maintaining a precise exception model. All

arithmetic instructions that execute in the core operate on data in the GPRs. Although the GPRs

are 64 bits wide, only SPE APU and embedded vector floating-point instructions operate on the

upper word of the GPRs; the upper 32 bits are not affected by 32-bit instructions.

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