MPC8540 datasheet(287/1302 Pages) FREESCALE

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MMU Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-37

6.12.5 MMU Assist Registers

6.12.5.1 MAS Register 0 (MAS0)

50–51

—

Reserved, should be cleared.

52–63

NENTRY

Number of entries in TLB1

0x010: TLB1 contains 16 entries

43 44

47 48

62 63

Field

—

TLBSEL

—

ESEL

—

Reset

All zeros

R/W

SPR

SPR 624

Figure 6-42. MAS Register 0 (MAS0)

Table 6-26. MAS0 Field Descriptions—MMU Read/Write and Replacement Control

Bits

Name

Descriptions

32–34

—

Reserved, should be cleared.

TLBSEL Selects TLB for access

0TLB0

1TLB1

36–43

—

Reserved, should be cleared.

44–47

ESEL

Entry select. Number of entry in selected array to be used for tlbwe. This field is also updated on

TLB error exceptions (misses), and tlbsx hit and miss cases.

For the e500, ESEL serves as the way select for the corresponding TLB as follows:

When TLBSEL = 00 (TLB0 selected), only bit 47 is used (and bits 44–46 should be cleared). This

bit selects between way 0 and way 1 of TLB0. EA bits 45–51 from MAS2[EPN] are used to index

into the TLB to further select the entry for the operation.

When TLBSEL = 01 (TLB1 selected), all four bits are used to select one of 16 entries in the array.

48–62

—

Reserved, should be cleared.

Next victim. Next victim bit value to be written to TLB0[NV] on execution of tlbwe. This field is also

updated on TLB error exceptions (misses), tlbsx hit and miss cases and on execution of tlbre.

This field is updated based on the calculated next victim bit for TLB0 (based on the round-robin

replacement algorithm.)

Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01).

Table 6-25. TLB1CFG Field Descriptions (continued)

Bits

Name

Description

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