MPC8540 datasheet(290/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-40

Freescale Semiconductor

Core Register Summary

6.12.5.4 MAS Register 3 (MAS3)

6.12.5.5 MAS Register 4 (MAS4)

51 52 53 54

Field

RPN

—

U0–U3

UX SX UW SW UR SR

Reset

All zeros

R/W

SPR

SPR 627

Figure 6-45. MAS Register 3 (MAS3)

Table 6-29. MAS3 Field Descriptions–RPN and Access Control

Bits

Name

Description

32–51

RPN

Real page number. Depending on page size, only the bits associated with a page boundary are

valid. Bits that represent offsets within a page are ignored and should be cleared.

52–53

—

Reserved, should be cleared.

54–57

U0–U3

User attribute bits. Associated with a TLB entry and can be used by system software. For example,

they can hold information useful to a page-scanning algorithm or mark more abstract page

attributes.

58–63

PERMI

Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute

permission bits.

51 52

55 56

Field

—

TLBSELD

—

TIDSELD

—

TSIZED

— X0D X1D WD ID MD GD ED

Reset

All zeros

R/W

SPR

SPR 628

Figure 6-46. MAS Register 4 (MAS4)

Table 6-30. MAS4 Field Descriptions—Hardware Replacement Assist

Configuration

Bits

Name

Description

32–34

—

Reserved, should be cleared.

TLBSELD TLBSEL default value. The default value to be loaded in MAS0[TLBSEL] on a TLB miss exception.

0TLB0

1TLB1

36–45

—

Reserved, should be cleared.

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