MPC8540 datasheet(294/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-44

Freescale Semiconductor

Core Register Summary

Table 6-33. DBCR1 Field Descriptions

Bits

Name

Description

32–33 IAC1US Instruction address compare 1 user/supervisor mode

00 IAC1 debug events can occur

01 Reserved

10 IAC1 debug events can occur only if MSR[PR] = 0

11 IAC1 debug events can occur only if MSR[PR] = 1

34–35 IAC1ER Instruction address compare 1 effective/real mode

00 IAC1 debug events are based on effective addresses

01 Reserved on the e500

10 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 0

11 IAC1 debug events are based on effective addresses and can occur only if MSR[IS] = 1

36–37 IAC2US Instruction address compare 2 user/supervisor mode

00 IAC2 debug events can occur

01 Reserved

10 IAC2 debug events can occur only if MSR[PR] = 0

11 IAC2 debug events can occur only if MSR[PR] = 1

38–39 IAC2ER Instruction address compare 2 effective/real mode

00 IAC2 debug events are based on effective addresses

01 Reserved on the e500

10 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 0

11 IAC2 debug events are based on effective addresses and can occur only if MSR[IS] = 1

40–41 IAC12M Instruction address compare 1/2 mode

00 Exact address compare. IAC1 debug events can occur only if the address of the instruction fetch

is equal to the value specified in IAC1. IAC2 debug events can occur only if the address of the

instruction fetch is equal to the value specified in IAC2.

01 Address bit match. IAC1 and IAC2 debug events can occur only if the address of the instruction

fetch, ANDed with the contents of IAC2 are equal to the contents of IAC1,plus ANDed with the

contents of IAC2.

If IAC1US

≠IAC2US or IAC1ER≠IAC2ER, results are boundedly undefined.

10 Inclusive address range compare. IAC1 and IAC2 debug events can occur only if the address of

the instruction fetch is greater than or equal to the value specified in IAC1 and less than the value

specified in IAC2.

If IAC1US

≠IAC2US or IAC1ER≠IAC2ER, results are boundedly undefined.

11 Exclusive address range compare. IAC1 and IAC2 debug events can occur only if the address

of the instruction fetch is less than the value specified in IAC1 or is greater than or equal to the

value specified in IAC2.

If IAC1US

≠IAC2US or IAC1ER≠IAC2ER, results are boundedly undefined.

42–63

—

Reserved, should be cleared.

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