MPC8540 datasheet(312/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-8

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Table 7-2 describes L2CTL fields.

Table 7-2. L2CTL Field Descriptions

Bits

Name

Description

L2E

L2 enable. Used to enable the L2 array (cache or memory-mapped SRAM).

0 The L2 SRAM (cache and memory-mapped SRAM) is disabled and is not accessed for reads,

snoops, or writes. Setting the L2 flash invalidate bit (L2I) is allowed.

1 The L2 SRAM (cache or memory-mapped SRAM) is enabled.

Note that L2I can be set regardless of the value of L2E.

L2I

L2 flash invalidate

0 The L2 status and LRU bits are not being cleared.

1 Setting L2I invalidates the L2 cache globally by clearing the all the L2 status bits, as well as the

LRU algorithm. Memory-mapped SRAM is unaffected.

Data in memory-mapped SRAM regions is unaffected by the flash invalidate. The hardware

automatically clears L2I when the invalidate is complete.

2–3

L2SIZ

L2 SRAM size (read only). Indicates the total available size of L2 SRAM (to be configured as cache

or memory-mapped SRAM).

00 Reserved

01 Reserved

10 256 Kbyte

11 Reserved

4–5

L2BLKSZ

L2 cache/memory-mapped SRAM block size. Determines the L2 cache/memory-mapped SRAM

block size. To change these bits, the L2 must be disabled (L2CTL[L2E] = 0). L2BLKSZ must be

≤

L2SIZ when L2E = 1. See the description of L2CTL[L2SRAM] for information on configuring the

total SRAM as cache or memory-mapped SRAM.

00 Reserved

01 128 Kbyte

10 256 Kbyte

11 Reserved

6–8

—

Reserved

L2DO

L2 data-only. Reserved in full memory-mapped SRAM mode. L2DO may be changed while the L2

is enabled or disabled.

0 The L2 cache allocates entries for instruction fetches that miss in the L2.

1 The L2 cache allocates entries for processor data loads that miss in the L2 and for processor L1

castouts but does not allocate entries for instruction fetches that miss in the L2. Instruction

accesses that hit in the L2, data accesses, and accesses from the system (including I/O stash

writes) are unaffected.

Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any

processor transactions, and processor writes and castouts that hit existing data in the cache

invalidate those lines rather than updating them.

L2IO

L2 instruction-only. Reserved in full memory-mapped SRAM mode. Causes the L2 cache to

allocate lines for instruction cache transactions only. L2IO may be changed while the L2 is enabled

or disabled.

0 The L2 cache entries are allocated for data loads that miss in the L2 and for processor L1

castouts.

1 The L2 cache allocates entries for instruction fetch misses, but does not allocate entries for

processor data transactions. Data accesses that hit in the L2, instruction accesses, and

accesses from the system (including I/O stash writes) are unaffected.

Note that if L2DO and L2IO are both set, no new lines are allocated into the L2 cache for any

processor transactions, and processor writes and castouts that hit existing data in the cache

invalidate those lines rather than updating them.

—

Reserved

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