MPC8540 datasheet(314/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-10

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

7.3.1.2

L2 Cache External Write Address Registers 0–3 (L2CEWARn)

The MPC8540 supports allocating and locking of L2 cache lines from external agents, such as PCI.

This functionality is called stashing. The L2 cache external write address registers 0–3

(L2CEWARn) are paired with the L2 cache external write control registers 0–3 (L2CEWCRn) to

control the cache external write functionality. Each register pair (for example, L2CEWAR0 and

L2CEWCR0) specifies a programmed memory range that can be locked with a snoop write

transaction. The address register must be naturally aligned to the window size in the corresponding

control register. L2CEWARn registers contain identical fields, as shown in Figure 7-8.

Table 7-3 describes L2CEWARn fields.

7.3.1.3

L2 Cache External Write Control Registers 0–3 (L2CEWCRn)

The L2CEWARn registers are paired with the L2 cache external write control registers 0–3

(L2CEWCRn), shown in Figure 7-9, to control cache external write functionality.

23 24

ADDR

0000

Reset

All zeros

Offset

0x2_0010, 0x2_0020, 0x2_0030, 0x2_0040

Figure 7-8. L2 Cache External Write Address Registers (L2CEWARn)

Table 7-3. L2CEWARn Field Descriptions

Bits

Nam

Description

0–23

ADD

L2 cache external write base address

24–3

—Reserved

ELOCK

000000

SIZMASK

Reset

All zeros

Offset

0x2_0018, 0x2_0028, 0x2_0038, 0x2_0048

Figure 7-9. L2 Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)

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