MPC8540 datasheet(191/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-5

– Perform a load of an address that does not access configuration space or the on-chip

SRAM, but has an address mapping already in effect (for example, boot ROM).

Follow this load with an isync.

– Read the contents of CCSRBAR from its new location, followed by another isync

instruction.

4.3.1.1.2

Configuration, Control, and Status Base Address Register

(CCSRBAR)

Figure 4-1 shows the fields of CCSRBAR.

Figure 4-1. Configuration, Control, and Status Register Base Address Register

(CCSRBAR)

Table 4-5 defines the bit fields of CCSRBAR.

4.3.1.2

Accessing Alternate Configuration Space

An alternate configuration space can be accessed by configuring the ALTCBAR and ALTCAR

registers. These are intended to be used with the boot sequencer to allow the boot sequencer to

access an alternate 1-Mbyte region of configuration space. By loading the proper boot sequencer

command in the serial ROM the base address in the ALTCBAR can be combined with the 20 bits

of address offset supplied from the serial ROM to generate a 32-bit address that is mapped to the

target specified in ALTCAR. Thus, by configuring these registers, the boot sequencer has access

to the entire memory map, one 1-Mbyte block at a time. See Section 11.4.5, “Boot Sequencer

Mode,” for more information.

10 11 12

2324 25 26 27 28293031

R 000 0

0 0 0 0

000

BASE_ADDR

000 00000

Reset

0000_0000_0000_1111_1111_0111_0000_0000

Offset

0x000

Table 4-5. CCSRBAR Field Descriptions

Bits

Name

Description

0–11

—

Write reserved, read = 0

12–23 BASE_ADDR Identifies the12 most-significant address bits of the window used for configuration accesses.

The base address is aligned on a 1-Mbyte boundary.

24–31

—

Write reserved, read = 0

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