MPC8540 datasheet(192/1302 Pages) FREESCALE

192 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-6

Freescale Semiconductor

Reset, Clocking, and Initialization

NOTE

The enable bit in the ALTCAR register should be cleared either by the

boot sequencer or by the boot code that executes after the boot

sequencer has completed its configuration operations. This prevents

problems with incorrect mappings if subsequent configuration of the

local access windows uses a different target mapping for the address

specified in ALTCBAR.

4.3.1.2.1

Alternate Configuration Base Address Register (ALTCBAR)

Figure 4-2 shows the fields of ALTCBAR.

Figure 4-2. Alternate Configuration Base Address Register (ALTCBAR)

Table 4-6 defines the bit fields of ALTCBAR.

4.3.1.2.2

Alternate Configuration Attribute Register (ALTCAR)

Figure 4-3 shows the fields of ALTCAR.

Figure 4-3. Alternate Configuration Attribute Register (ALTCAR)

1112

2324

R 0

000

BASE_ADDR

000

0000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x008

Table 4-6. ALTCBAR Field Descriptions

Bits

Name

Description

0–11

—

Write reserved, read = 0

12–23 BASE_ADDR Identifies the12 most-significant address bits of an alternate window used for configuration

accesses.

24–31

—

Write reserved, read = 0

4567

30 31

0000

TRGT_ID

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x010

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