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MFS5600AMBA0ES 데이터시트(PDF) 108 Page - NXP Semiconductors

부품명 MFS5600AMBA0ES
상세설명  Automotive buck regulator and controller with voltage monitors and watchdog timer
PDF  111 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS5600AMBA0ES 데이터시트(HTML) 108 Page - NXP Semiconductors

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NXP Semiconductors
FS5600
Automotive buck regulator and controller with voltage monitors and watchdog timer
Tables
Tab. 1.
Device options ...................................................2
Tab. 2.
Ordering information ..........................................3
Tab. 3.
Pin description ...................................................6
Tab. 4.
ESD ratings .......................................................8
Tab. 5.
Temperature range ............................................8
Tab. 6.
QFN32 thermal resistance and package
dissipation ratings ............................................. 8
Tab. 7.
Device level electrical parameters .....................9
Tab. 8.
SW1 electrical specifications ...........................10
Tab. 9.
SW1 external component selection .................11
Tab. 10. OTP_SW1_VOLT[7:0] selection ...................... 12
Tab. 11. OTP_SW1_MIN_TON[1:0] selection ............... 15
Tab. 12. SW1_MODE[1:0] selection. .............................15
Tab. 13. OTP_SW1_PFM_TON[1:0] selection .............. 16
Tab. 14. SW1 compensation selection ..........................16
Tab. 15. OTP_SW1_SLOPECOMP[1:0] Value ..............17
Tab. 16. OTP_SW1_GM_COMP[1:0] Value ..................17
Tab. 17. OTP_SW1_PWM_R_COMP[2:0] Value .......... 17
Tab. 18. SW2 electrical characteristics ......................... 19
Tab. 19. SW2 recommended external components .......20
Tab. 20. MOSFET selection .......................................... 21
Tab. 21. SW2 Compensation selection ......................... 21
Tab. 22. OTP_SW2_VOLT[5:0] Selection ..................... 23
Tab. 23. OTP_SW2_TON_MIN[1:0] Selection ...............25
Tab. 24. SW2_MODE[2:0] selection ..............................25
Tab. 25. OTP_SW2_PFM_TON[1:0] Selection ..............26
Tab. 26. OTP_SW2_SLOPECOMP[5:0] selection .........26
Tab. 27. FS5600 clock electrical characteristics ............29
Tab. 28. Internal oscillator frequency selection ............. 30
Tab. 29. SW1 and SW2 switching frequency
selection .......................................................... 31
Tab. 30. I/O pin electrical specifications ........................32
Tab. 31. PGOOD1/2, GPIO1/2/3 delay selection .......... 34
Tab. 32. I2C address selection ......................................35
Tab. 33. Thermal protection characteristics ...................35
Tab. 34. GPIO1 function selection ................................ 36
Tab. 35. GPIO2 function selection ................................ 36
Tab. 36. GPIO3 function selection ................................ 37
Tab. 37. VMON1-4 electrical specifications ...................37
Tab. 38. Watchdog window period configuration ...........40
Tab. 39. Watchdog window duty cycle configuration ..... 41
Tab. 40. Watchdog error counter ...................................42
Tab. 41. WD_FAIL_IMPACT[1:0] description .................42
Tab. 42. Watchdog refresh counter configuration ..........43
Tab. 43. FCCU1/2 status reporting error scenarios .......45
Tab. 44. ERRMON acknowledge timer selection .......... 46
Tab. 45. PGOOD1/2 programmable reactions .............. 47
Tab. 46. FS0B pin electrical specifications ....................48
Tab. 47. List of registers modifiable only during
INIT_RUN state ...............................................50
Tab. 48. INIT_RUN protected registers after first
WD_OK if watchdog enabled. ......................... 50
Tab. 49. FLT_ERR_CNT_LIMIT[1:0] description ........... 51
Tab. 50. Fault counter source assignment .................... 51
Tab. 51. ABIST flag bits ................................................ 52
Tab. 52. POR Thresholds ..............................................54
Tab. 53. State transition table ....................................... 57
Tab. 54. I2C register map ............................................. 61
Tab. 55. FS5600 register map bit-types ........................ 68
Tab. 56. SW1CTRL register description ........................68
Tab. 57. NOT_SW1CTRL register description .............. 68
Tab. 58. SW2CTRL register description ........................69
Tab. 59. NOT_SW2CTRL register description .............. 69
Tab. 60. GPIO_CTRL register description .....................69
Tab. 61. NOT_GPIO_CTRL register description ........... 70
Tab. 62. CLOCK_CTRL register description ................. 71
Tab. 63. NOT_CLOCK_CTRL register description ........71
Tab. 64. WATCHDOG_CTRL1 register description .......72
Tab. 65. NOT_WATCHDOG_CTRL1 register
description ....................................................... 73
Tab. 66. WATCHDOG_CTRL2 register description .......74
Tab. 67. NOT_WATCHDOG_CTRL2 register
description ....................................................... 74
Tab. 68. WATCHDOG_SEED register description .........75
Tab. 69. WATCHDOG_ANSWER register
description ....................................................... 75
Tab. 70. OD_ABIST_CTRL register description ............ 75
Tab. 71. NOT_OD_ABIST register description ..............75
Tab. 72. BIST_STATUS1 register description ................75
Tab. 73. BIST_STATUS2 register description ................77
Tab. 74. FAULT_CTRL register description ...................78
Tab. 75. NOT_FAULT_CTRL register description ......... 79
Tab. 76. VMON_STS register description ..................... 79
Tab. 77. VMON_RT register description ....................... 80
Tab. 78. GPIO_STS register description ....................... 82
Tab. 79. FCCU_CFG register description ..................... 83
Tab. 80. NOT_FCCU_CFG register description ............ 83
Tab. 81. STATE_CTRL register description ...................84
Tab. 82. NOT_STATE_CTRL register description ......... 84
Tab. 83. STATE register description ..............................85
Tab. 84. ID1 register description ................................... 85
Tab. 85. Revision history .............................................105
Figures
Fig. 1.
FS5600 Functional block diagram .....................2
Fig. 2.
FS5600 internal block diagram ......................... 4
Fig. 3.
Regulator input options ..................................... 4
Fig. 4.
QM version pinout .............................................5
Fig. 5.
ASIL B, and enhanced ASIL B version
pinout .................................................................5
Fig. 6.
SW1 high-level block diagram .........................10
Fig. 7.
SW1 output voltage setting using an
external resistor divider ...................................12
Fig. 8.
SW2 high-level block diagram .........................19
Fig. 9.
SW2 application schematic with Rshunt
current sensing ................................................22
FS5600
All information provided in this document is subject to legal disclaimers.
© 2022 NXP B.V. All rights reserved.
Product data sheet
Rev. 3 — 2 August 2022
108 / 111



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