DP83848-HT datasheet(13/81 Pages) TI

13 / 81 page

(T/R)

IDLE

DATA

PMD input pair

CRS

T2.10.1

(J/K)

IDLE

DATA

PMD input pair

CRS

RXD[3:0]

RX_DV

RX_ER

T2.9.1

T2.9.2

DP83848-HT

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SLLSEJ7 – FEBRUARY 2015

Table 9. 100BASE-TX Receive Packet Latency Timing

PARAMETER(1)

NOTES(2)(3)

MIN

TYP

MAX

UNIT

T2.9.1

Carrier sense ON delay

100 Mb/s normal mode

bits

T2.9.2

Receive data latency

100 Mb/s normal mode

bits

(1)

Carrier sense ON delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(2)

1 bit time = 10 ns in 100 Mb/s mode.

(3)

PMD input pair voltage amplitude is greater than the signal detect turn-on threshold value.

Figure 9. 100BASE-TX Receive Packet Latency Timing

Table 10. 100BASE-TX Receive Packet Deassertion Timing

PARAMETER

NOTES(1)(2)

MIN

TYP

MAX

UNIT

T2.10.1

Carrier sense OFF delay

100 Mb/s normal mode

bits

(1)

Carrier sense off delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of carrier sense.

(2)

1 bit time = 10 ns in 100 Mb/s mode

Figure 10. 100BASE-TX Receive Packet Deassertion Timing

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