| 전자부품 데이터시트 검색엔진 |
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24LLC02 데이터시트(PDF) 15 Page - Ceramate Technical |
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24LLC02 데이터시트(HTML) 15 Page - Ceramate Technical |
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15 / 19 page ![]() 24LLC02 2K-Bits Serial EEPROM For Low Power * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 15 of 19 Rev 1.0 Dec. 26, 2001 Table 1-4. D.C. Electrical Characteristics (Continued) (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V CC = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance C IN 25 °C, 1MHz, V CC = 5 V, V IN = 0 V, A0, A1, A2, SCL and WP pin – – 10 pF Input/output capacitance C I/O 25 °C, 1MHz, V CC = 5 V, V I/O = 0 V, SDA pin – – 10 Table 1-5. A.C. Electrical Characteristics (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V CC = 1.8 V to 5.5 V) Parameter Symbol Conditions V CC = 1.8 to 5.5 V (Standard Mode) V CC = 2.5 to 5.5 V (Fast Mode) Unit Min Max Min Max External clock frequency F CLK – 0 100 0 400 kHz Clock high time tHIGH – 4 – 0.6 – µs Clock low time tLOW – 4.7 – 1.3 – Rising time tR SDA, SCL – 1 – 0.3 Falling time tF SDA, SCL – 0.3 – 0.3 Start condition hold time tHD:STA – 4 – 0.6 – Start condition setup time tSU:STA – 4.7 – 0.6 – Data input hold time tHD:DAT – 0 – 0 – Data input setup time tSU:DAT – 0.25 – 0.1 – Stop condition setup time tSU:STO – 4 – 0.6 – Bus free time tBUF Before new transmission 4.7 – 1.3 – Data output valid from clock low (note) tAA – 0.3 3.5 – 0.9 Noise spike width tSP – – 100 – 50 ns Write cycle time tWR – – 5 – 5 ms NOTES : 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the 24LLC02 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. |
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