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48LM01 데이터시트(PDF) 15 Page - Microchip Technology

부품명 48LM01
상세설명  512-Kbit/1-Mbit SPI Serial EERAM
PDF  40 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

48LM01 데이터시트(HTML) 15 Page - Microchip Technology

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 2018-2019 Microchip Technology Inc.
DS20006008C-page 15
48L512/48LM01
6.2
Write Enable Latch
Enabling and disabling writing to the STATUS register,
Memory Partition register, Under-Voltage Lockout
register and the SRAM array is accomplished through
the Write Enable (WREN) instruction as shown in
Section 5.1 "Write Enable Instruction (WREN)" and
the Write Disable (WRDI) instruction as shown in
Section 5.2 "Write Disable Instruction (WRDI)".
These functions change the status of the WEL bit (bit 1)
in the STATUS register.
6.3
Ready/Busy Status Latch
The Ready/Busy Status Latch is used to indicate
whether the device is currently active in a nonvolatile
write operation. This bit is read-only and automatically
updated by the device. This bit is provided in bit posi-
tion ‘0’.
A logic ‘1’ bit indicates that the device is currently busy
performing an SRAM to EEPROM transfer or EEPROM
to SRAM restore operation. During this time, only the
Read STATUS Register (RDSR) command will be exe-
cuted by the device.
A logic ‘0’ bit in this position indicates the device is
ready to accept new SRAM Read/Write commands.
6.4
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction
provides access to the contents of the STATUS
register. The STATUS register is read by asserting the
CS pin followed by sending in a 05h opcode. The
device will return the 8-bit STATUS register value on
the SO pin.
The STATUS register can be continuously read for data
by continuing to read beyond the first 8-bit value
returned. The 48L512/48LM01 will update the STATUS
register value upon the completion of every eight bits,
thereby allowing new STATUS register values to be
read without having to issue a new RDSR instruction.
FIGURE 6-1:
RDSR WAVEFORM
TABLE 6-2:
BLOCK WRITE-PROTECT BITS
Level
STATUS Register Bits [3:2]
Protected Address Range
BP1
BP0
48L512
48LM01
0
00
None
None
1
01
C000-FFFF
18000-1FFFF
2
10
8000-FFFF
10000-1FFFF
3
11
0000-FFFF
00000-1FFFF
SI
910 11
14 15
SCK
0
2
3
4
5
6
7
1
8
000
00
101
RDSR Opcode
12 13
DD
D
DDD D D
STATUS Register
SO
CS
High-Impedance



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