DRA821U2...ALM datasheet(93/252 Pages) TI

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Table 6-108. Reserved Balls Specific Connection Requirements (continued)

BALLS

CONNECTION REQUIREMENTS

H18 / F18 / N18 / L20 / K20 / J20 / V8 / V10 / E5 / F6

These balls must be left unconnected.

Note

All other unused signal balls without Pad Configuration Register can be left unconnected.

Note

All other unused signal balls with a Pad Configuration Register can be left unconnected with their

multiplexing mode set to GPIO input and internal pulldown resistor enabled.

Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case

where internal pull resistors are allowed as the only source/sink to hold a valid logic level.

Any balls connected to a via, test point, or PCB trace are considered used and must not depend on

the internal pull resistor to hold a valid logic level.

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for

some operating conditions. This may be the case when connected to components with leakage to the

opposite logic level, or when external noise sources couple to signal traces attached to balls which

are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be

required to hold a valid logic level on balls with external connections.

If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state

which could damage the IO cell.

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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DRA821U2...ALM 데이터시트(PDF) 93 Page - Texas Instruments