DRA821U2...ALM datasheet(96/252 Pages) TI

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Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power

supply voltage. This allows external voltage sources to be connected to these IO terminals when the

respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,

MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn, MCU_PORz, PORz, VMON1_ER_VSYS, VMON2_IR_VCPU,

VMON3_IR_VEXT1P8, VMON4_IR_VEXT1P8, VMON5_ER_VEXT3P3 are the only fail-safe IO terminals. All

other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the

Steady State Max. Voltage at all IO pins parameter in Section 7.1.

overshoot

undershoot

period

Overshoot = 20% of nominal

IO supply voltage

Undershoot = 20% of nominal

IO supply voltage

Tovershoot + Tundershoot < 20% of Tperiod

Figure 7-1. IO Transient Voltage Ranges

7.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

±1000

Charged-device model (CDM), per AEC Q100-011

All pins

±250

Corner pins (A1,

AJ29)

±750

(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME

DESCRIPTION

MIN

(1)

NOM

MAX

(1)

UNIT

VDD_CORE(3)

Boot/Active voltage for MAIN domain core supply

0.76

0.8

0.84

VDD_MCU

Boot/Active voltage for MCUSS core supply

0.76

0.8

0.89

VDD_CPU

Boot voltage for CPU core supply, applied at cold

power up event

0.76

0.8

0.84

Active voltage for CPU core supply, after AVS mode

enabled in software

AVS

(5)-5%

AVS

(5)

AVS

(5)+5%

VDD_CPU AVS Range

Efuse valid voltage range for VDD_CPU voltage

0.6

0.9

VDD_MCU_WAKE1

Core supply for MCU WAKE function

0.76

0.8

0.89

VDD_WAKE0

Core supply for MAIN domain WAKE function which

includes all "CANUART" IO.

0.76

0.8

0.89

VDDA_0P8_DLL_MMC0

MMC PLL analog supply

0.76

0.8

0.84

VDDAR_CORE

Main domain RAM supply

0.81

0.85

0.89

VDDAR_MCU

MCUSS RAM supply

0.81

0.85

0.89

VDDAR_CPU

CPU RAM supply

0.81

0.85

0.89

VDDA_0P8_SERDES0(3)

SERDES0 analog supply low

0.76

0.8

0.84

VDDA_0P8_SERDES0_C(3)

SERDES0-1 clock supply

0.76

0.8

0.84

VDDA_0P8_USB(3)

USB 0.8v analog supply

0.76

0.8

0.84

VDDA_1P8_USB

USB 1.8v analog supply

1.71

1.8

1.89

VDDA_1P8_SERDES0

SERDES0 analog supply high

1.71

1.8

1.89

VDDA_3P3_USB

USB 3.3v analog supply

3.14

3.3

3.46

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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