DRA821U2...ALM datasheet(112/252 Pages) TI

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7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing

Figure 7-4 describes the device power-down sequencing.

J7VCL_ELCH_02

VDD_CPU

MCU_PORz

(J)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

Δ1

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) , VDDA_3P3_USB

(D) (B)

(E)

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) ,VDDS_MMC0

(D) (C)

VDD_MCU , VDD_MCU_WAKE1, VDD_CORE,

(I)

VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB,

VDDAR_CORE, VDDAR_CPU, VDDAR_MCU

(I)

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0

(H)

(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,

VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,

VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)

(F)

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(G)

PORz

(J)

Valid Configuration

Terminology:

•

Primary = Essential power down sequence of all voltage domains to complete off state.

•

VOPR MIN = Minimum operational voltage level that ensures functionality as specified in , Recommended Operating Conditions.

•

Ramp-down = voltage supply transition time from VOPR MIN to off condition.

•

Domain_“n” = multiple instances of similar voltage domains (that is, dual voltage IO domains, VDDSHVn = VDDSHV0, VDDSHV1,

VDDSHV2 … VDDSHV6)

•

Domain_“xxx” = different signal type/protocol domains using same voltage supply type and level (that is, VDDA_1P8_xx =

VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

Time stamps:

Markers showing approximate elapsed times that are dependent upon PDN feature set, component selection and power mapping.

Values shown are typical for PDNs combining MCU and Main voltage domains but could vary based upon PDN design.

Time Stamp definitions and (typical values for reference only):

T0 – MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)

T1 – Main DDR, SRAM Core and SRAM CPU power domains start ramp-down. (0.5 ms)

T2 – All core voltages start supply ramp-down. (2.5 ms)

T3 – All 1.8V voltages start supply ramp-down. (3.0 ms)

T4 – All 3.3-V voltages start supply ramp-down. (3.5 ms)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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