 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
DRA821U2...ALM 데이터시트(PDF) 143 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRA821U2...ALM 데이터시트(HTML) 143 Page - Texas Instruments |
|
|
143 / 252 page  7.9.4.2 Output Clocks The device provides several system clock outputs. Summary of these output clocks are as follows: • MCU_CLKOUT0 – Reference clock output for Ethernet PHYs (50 MHz or 25 MHz) • MCU_SYSCLKOUT0 – SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not. • MCU_OBSCLK0 – On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug. • SYSCLKOUT0 – SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not. • CLKOUT – Reference clock output • OBSCLK[2:0] – On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug. www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: DRA821U-Q1 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
