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DRA821U2...ALM 데이터시트(PDF) 148 Page - Texas Instruments

부품명 DRA821U2...ALM
상세설명  DRA821 Jacinto™ Processors
PDF  252 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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DRA821U2...ALM 데이터시트(HTML) 148 Page - Texas Instruments

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RMII[x]_TXD[1:0],
RMII[x]_TXEN (outputs)
SPRSP08_CPSW2G_RMIITX
RMII6
RMII7
RMII[x]_REFCLK (input)
RMII8
Figure 7-41. SPI Master Mode Receive Timing
7.9.5.2.2 CPSW2G RGMII Timings
Section 7.9.5.2.2.1, Section 7.9.5.2.2.2, and Figure 7-42 present timing requirements for receive RGMII
operation.
7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
TYP
MAX
UNIT
RGMII1 tc(RXC)
Cycle time, RXC
10Mbps
360
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
RGMII2 tw(RXCH)
Pulse duration, RXC high
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
RGMII3 tw(RXCL)
Pulse duration, RXC low
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
RGMII4 tt(RXC)
Transition time, RXC
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
TYP
MAX
UNIT
RGMII5 tsu(RD-RXC)
Setup time, RD[3:0] valid before RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
tsu(RX_CTL-RXC)
Setup time, RX_CTL valid before RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
RGMII6 th(RXC-RD)
Hold time, RD[3:0] valid after RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
th(RXC-RX_CTL)
Hold time, RX_CTL valid after RXC high/low
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
148
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Product Folder Links: DRA821U-Q1



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