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• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must

be approximately equal to the signal propagation delay of the control and data signals between the flash

device and the SoC device (E to F, or F to E)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-3

• Propagation delays and matching:

– A to B = E to F = (C to D) / 2

– Matching skew: < 60 ps

Note

The OSPI Board Loopback Hold time requirement (described in Section 7.9.5.18, OSPI) is larger than

the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin

to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.

MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

Device Clock Input

OSPI/QSPI/SPI

Device IO[y], CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

MCU_OSPI_Board_02

MCU_OSPI[x]_LBCLKO

MCU_OSPI[x]_DQS

OSPI Device DQS

* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine

tuning, if needed.

Figure 9-3. OSPI Interface High Level Schematic

9.3.2.3 DQS (only available in Octal Flash devices)

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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DRA821U2...ALM 데이터시트(PDF) 234 Page - Texas Instruments