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TDA4VE...ALZQ1 데이터시트(PDF) 100 Page - Texas Instruments

부품명 TDA4VE...ALZQ1
상세설명  TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0
PDF  251 Pages
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7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
MIN
MAX
UNIT
Latch-up Performance, Class II (125°C)(4)
I-Test
–100
100
mA
Over-Voltage (OV)
Test
NA
1.5 × VDD(6)
V
TSTG (5)
Storage temperature
–55
+150
°C
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2)
All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.
(3)
This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(4)
For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.
(5)
For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
(6)
VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(7)
The VMON pins provides a way to monitor the system power supply. For more information, see System Power Supply Monitor Design
Guidelines using VMON/POK.
(8)
An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design
Guidelines.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The specific signals that are fail safe are highlighted in the parameter "Steady
State Max. Voltage at all fail-safe IO pins". All other IO terminals are not fail-safe and the voltage applied to
them should be limited to the value defined by the "Steady State Max. Voltage at all other IO pins" parameter in
Absolute Maximum Ratings.
T
overshoot
T
undershoot
T
period
Overshoot = 20% of nominal
IO supply voltage
Undershoot = 20% of nominal
IO supply voltage
A.
Tovershoot + Tundershoot < 20% of Tperiod
Figure 7-1. IO Transient Voltage Ranges
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±1000
V
Charged-device model (CDM), per AEC Q100-011
All pins
±250
Corner pins (A1,
AJ29)
±750
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1
SPRSP62 – DECEMBER 2022
www.ti.com
100
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1



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