TDA4VE...ALZQ1 datasheet(230/251 Pages) TI

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For more details about features and additional description information on the device Universal Serial Bus

Subsystem (USB), see the corresponding sections within Signal Descriptions and Detailed Description.

7.10.6 Emulation and Debug

7.10.6.1 Trace

Table 7-92. Trace Timing Conditions

PARAMETER

MIN

MAX

UNIT

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch)

Propagation delay mismatch across

all traces

200

Table 7-93 and Figure 7-111 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 7-93. Trace Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

1.8 V Mode

DBTR1

tc(TRC_CLK)

Cycle time, TRC_CLK

6.50

DBTR2

tw(TRC_CLKH)

Pulse width, TRC_CLK high

2.50

DBTR3

tw(TRC_CLKL)

Pulse width, TRC_CLK low

2.50

DBTR4

tosu(TRC_DATAV-TRC_CLK)

Output setup time, TRC_DATA valid to TRC_CLK edge

0.81

DBTR5

toh(TRC_CLK-TRC_DATAI)

Output hold time, TRC_CLK edge to TRC_DATA invalid

0.81

DBTR6

tosu(TRC_CTLV-TRC_CLK)

Output setup time, TRC_CTL valid to TRC_CLK edge

0.81

DBTR7

toh(TRC_CLK-TRC_CTLI)

Output hold time, TRC_CLK edge to TRC_CTL invalid

0.81

3.3 V Mode

DBTR1

tc(TRC_CLK)

Cycle time, TRC_CLK

9.75

DBTR2

tw(TRC_CLKH)

Pulse width, TRC_CLK high

4.13

DBTR3

tw(TRC_CLKL)

Pulse width, TRC_CLK low

4.13

DBTR4

tosu(TRC_DATAV-TRC_CLK)

Output setup time, TRC_DATA valid to TRC_CLK edge

1.22

DBTR5

toh(TRC_CLK-TRC_DATAI)

Output hold time, TRC_CLK edge to TRC_DATA invalid

1.22

DBTR6

tosu(TRC_CTLV-TRC_CLK)

Output setup time, TRC_CTL valid to TRC_CLK edge

1.22

DBTR7

toh(TRC_CLK-TRC_CTLI)

Output hold time, TRC_CLK edge to TRC_CTL invalid

1.22

TRC_DATA

TRC_CTL

TRC_CLK

(

)

(

)

(Ideal)

Worst Case 1

Worst Case 2

DBTR1

DBTR2

DBTR3

DBTR4

DBTR6

DBTR5

DBTR7

DBTR4

DBTR6

DBTR5

DBTR7

SPRSP08_Debug_01

Figure 7-111. Trace Switching Characteristics

7.10.6.2 JTAG

For more details about features and additional description information on the device IEEE 1149.1 Standard–

Test–Access Port, see the corresponding sections within Signal Descriptions and Detailed Description.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1

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