AD74115BCPZ datasheet(64/103 Pages) AD

64 / 103 page

Data Sheet

AD74115

THEORY OF OPERATION

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Rev. 0 | 64 of 103

contribute off-leakage to the screw terminal when not in use. This

leakage can affect the accuracy of the analog functions, especially

to RTD measurements.

The AD74115 has a FET leakage compensation feature that pro-

vides an alternative path to the FET leakage to prevent it from

flowing in the I/OP screw terminal.

To enable this feature, configure the FET_LKG_COMP register. Set

the FET_SRC_LKG_COMP_EN bit for sourcing digital output and

set the FET_SNK_LKG_COMP_EN bit for sinking digital output.

For sourcing the digital output, connect the DO_SRC_INT pin to

the drain of the FET as shown in Figure 52. Similarly, for sinking

the digital output, connect the DO_SNK_INT pin to the drain of the

sinking FET as shown in Figure 53.

The FET leakage compensation feature can be used if the specified

leakage of the chosen external FET is expected to contribute error

to the precision analog measurements like the current input or

3-wire and 4-wire RTD measurements. This feature is not recom-

mended for use in 2-wire RTD mode.

Figure 52. Configuration for Digital Output Sourcing with FET Leakage Compensation

Figure 53. Configuration for Digital Output Sinking with FET Leakage Compensation

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