74ALVT16260 datasheet(2/14 Pages) PHILIPS

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Philips Semiconductors

Product specification

74ALVT16260

2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches

(3-State)

1998 Jan 30

853-2046-18918

FEATURES

• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;

exceeds 200V using machine model

• Latch-up protection exceeds 500mA per JEDEC Standard

JESD-17.

• Distributed V

CC and GND pin configuration minimizes high-speed

switching noise.

• Output capability (–32mA I

OH, 64mA IOL).

• Bus hold inputs eliminate the need for external pull-up resistors.

• 5V I/O compatible

• Live insertion/extraction permitted

• Power-up 3-State

• Power-up Reset

DESCRIPTION

The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used

in applications where two separate data paths must be multiplexed

onto, or demultiplexed from, a single data path. Typical applications

include multiplexing and/or demultiplexing of address and data

information in microprocessor or bus-interface applications. This

device is alto useful in memory-interleaving applications.

Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are

available for address and/or data transfer. The output enable (OE1B,

OE2B, and OEA) inputs control the bus transceiver functions. The

OE1B and OE2B control signals also allow bank control in the A to

B direction.

Address and/or data information can be stored using the internal

storage latches. The latch enable (LE1B, LE2B, LEA1B, and

LEA2B) inputs are used to control data storage. When the latch

enable input is high, the latch is transparent. When the latch enable

input goes low, the data present at the inputs is latched and remains

latched until the latch enable input is returned high.

To ensure the high-impedance state during power-up or

power-down, OE should be tied to VCC through a pull-up resistor;

the minimum value of the resistor is determined by the current

sinking capability of the driver.

The 74ALVT16260 is available in a 56-pin Shrink Small Outline

Package (SSOP) and 56-pin Thin Shrink Small Outline Package

(TSSOP).

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

SYMBOL

PARAMETER

Tamb = 25°C; GND = 0V

2.5V

3.3V

UNIT

tPLH

Propagation delay

C =50 pF

3.5

2.8

tPHL

nAx to nBx

nBx to nAx

CL = 50 pF

3.3

2.6

CIN

Input capacitance

VI = 0 V or VCC

COUT

Output capacitance

VI/O = 0 V or 5.0 V

ICCZ

Total supply current

Outputs disabled

100

µA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

56-Pin Plastic SSOP Type III

–40

°C to +85°C

74ALVT16260 DL

AV16260 DL

SOT371-1

56-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVT16260 DGG

AV16260 DGG

SOT364-1

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