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DS20005156B-page 13

23LCV1024

4.0

DUAL SERIAL MODE

The 23LCV1024 also supports Serial Dual (SDI) mode

of operation when used with compatible host devices.

As a convention for SDI mode of operation, two bits are

entered per clock using the SIO0 and SIO1 pins. Bits

are clocked MSb first.

4.1

Dual Interface Mode

The 23LCV1024 supports Serial Dual (SDI) mode of

operation. To enter SDI mode, the EDIO command

must be clocked in (see Figure 4-1). It should be noted

that if the microcontroller resets before the SRAM, the

user will need to determine the serial mode of operation

of the SRAM and reset it accordingly. Byte read and

write sequence in SDI mode is shown in Figure 4-2 and

Figure 4-3.

FIGURE 4-1:

ENTER SDI MODE (EDIO) FROM SPI MODE

FIGURE 4-2:

BYTE READ MODE SDI

SCK

0

2

3

4567

1

SI

High-Impedance

SO

CS

00

0

111

1

1

Note 1: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is

brought high.

2: The first byte read after the address will be a dummy byte.

CS

14 15 16 17 18 19 20 21 22 23

02

3

45

6

1

42

0

22 20 18

53 1

23 21 19

24-Bit Address

Instruction

Dummy Byte

64 2 0

75 3 1

Data Out

SCK

SIO0

SIO1

1

0

0

0

00 0 1

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