| 전자부품 데이터시트 검색엔진 |
|
74ALVT16652DGG 데이터시트(PDF) 2 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
74ALVT16652DGG 데이터시트(HTML) 2 Page - NXP Semiconductors |
|
2 / 14 page ![]() Philips Semiconductors Product specification 74ALVT16652 2.5V/3.3V 16-bit bus transceiver/register (3-State) 2 1998 Feb 13 853-1854 18962 FEATURES • 16–bit bus interface • 5V I/O Compatible • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ALVT16652 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. The device can be used as two 8-bit transceivers or one 16-bit transceiver. Complimentary output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A Low-input level selects real-time data, and a High input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Data on the A or B bus, or both, can be stored in the internal flip-flops by Low-to-High transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYPICAL UNIT SYMBOL PARAMETER Tamb = 25°C 2.5V 3.3V UNIT tPLH tPHL Propagation delay nAx to nBx or nBx to nAx CL = 50pF 2.0 2.1 1.5 1.6 ns CIN Input capacitance DIR, OE VI = 0V or VCC 3 3 pF CI/O I/O pin capacitance VI/O = 0V or VCC 9 9 pF ICCZ Total supply current Outputs disabled 40 70 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVT16652 DL AV16652 DL SOT371-1 56-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVT16652 DGG AV16652 DGG SOT364-1 LOGIC SYMBOL (IEEE/IEC) 56 1 55 54 2 5 6 8 9 10 12 13 14 3 EN1(BA) EN2(AB) C3 G4 C5 G6 w1 1 5D 6 16 43D 4 1 w1 2 52 51 49 48 47 45 44 43 29 28 30 31 27 26 15 16 17 19 20 21 23 24 42 41 40 38 37 36 34 33 w1 7 11D 12 1 12 10 9D 10 1 w1 8 EN7(BA) EN8(AB) C9 G10 C11 G12 SW00158 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |