| 전자부품 데이터시트 검색엔진 |
|
PCF8576DH/2 데이터시트(PDF) 25 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCF8576DH/2 데이터시트(HTML) 25 Page - NXP Semiconductors |
|
25 / 41 page ![]() 2004 Dec 22 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is lost accidentally, for example, by noise in adverse electrical environments, or if the LCD multiplex drive mode is changed in an application using several cascaded PCF8576Ds, as the drive mode cannot be changed on all of the cascaded devices simultaneously. SYNC can be either an input or an output signal; a SYNC output is implemented as an open-drain driver with an internal pull-up resistor. A PCF8576D asserts SYNC at the start of its last active backplane signal, and monitors the SYNC line at all other times. If cascade synchronization is lost, it will be restored by the first PCF8576D to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for each LCD drive mode is shown in Fig.20. Table 14 SYNC contact resistance The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14. NUMBER OF DEVICES MAXIMUM CONTACT RESISTANCE 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 10 to 16 700 Ω handbook, full pagewidth HOST MICRO- PROCESSOR/ MICRO- CONTROLLER SDA SCL CLK OSC SYNC 1, 58, 59 2, 3 4 5 7 89 6 8 9 10 11 12 13 10 11 12 40 segment drives 4 backplanes 40 segment drives LCD PANEL (up to 2560 elements) PCF8576DU A0 A1 A2 SA0 VDD VLCD DD V LCD V MDB077 SDA SCL SYNC CLK OSC 1, 58, 59 613 2, 3 4 5 7 BP0 to BP3 (open-circuit) A0 A1 A2 SA0 VSS VSS VSS VDD VLCD PCF8576DU BP0 to BP3 R tr 2CB ≤ Fig.19 Cascaded PCF8576D configuration. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |