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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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KSZ9567RTXI-TR 데이터시트(PDF) 167 Page - Microchip Technology |
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KSZ9567RTXI-TR 데이터시트(HTML) 167 Page - Microchip Technology |
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167 / 232 page  2017-2019 Microchip Technology Inc. DS00002329D-page 167 KSZ9567R 5.2.6.16 Port ACL Access F Register 5.2.6.17 Port ACL Byte Enable MSB Register 5.2.6.18 Port ACL Byte Enable LSB Register Address: 0xN60F Port N: 1-7 Size: 8 bits Bits Description Type Default 7:0 Ruleset [7:0] R/W 0x00 Address: 0xN610 Port N: 1-7 Size: 8 bits Bits Description Type Default 7:0 Byte Enable [15:8] Each bit enables accessing one of the ACL bytes when a read or write is initiated by writing to the Port ACL Byte Enable LSB Register. Bit 0 applies to the Port ACL Access 7 Register Bit 1 applies to the Port ACL Access 6 Register, etc. Bit 7 applies to the Port ACL Access 0 Register 1 = Byte is selected for read/write 0 = Byte is not selected R/W 0x00 Address: 0xN611 Port N: 1-7 Size: 8 bits Bits Description Type Default 7:0 Byte Enable [7:0] Each bit enables accessing one of the ACL bytes when a read or write is initiated by writing to the Port ACL Byte Enable LSB Register. Bit 0 applies to the Port ACL Access F Register Bit 1 applies to the Port ACL Access E Register, etc. Bit 7 applies to the Port ACL Access 8 Register 1 = Byte is selected for read/write 0 = Byte is not selected R/W 0x00 |
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