UPSD3422_V01 datasheet(74/300 Pages) STMICROELECTRONICS

74 / 300 page

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Power saving modes

UPSD3422, UPSD3433, UPSD3434, UPSD3454

74/300

Table 31.

MCU module port and peripheral status during reduced power modes

Mode

Ports 1, 3, 4

SPI, I2C,

UART0,1

PCA,

Timer

0,1,2

USB

ADC

EXT

INT0,1

Supervisory

Idle

Maintain

data

Active

Active(1)

The Watchdog Timer is not active during Idle mode. Other supervisor functions are active: LVD, external

reset, JTAG Debug reset.

Power-

down

Maintain

data

Disabled

Table 32.

State of 8032 MCU bus signals during power-down and idle modes

Mode

ALE

PSEN_

RD_

WR_

AD0-7

A8-15

Idle

0111

FFh

Power-down

0111

FFh

Table 33.

PCON: power control register (SFR 87h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMOD0

SMOD1

–

POR

RCLK1

TCLK1

IDL

Table 34.

PCON register bit definition

Bit

Symbol

R/W

Function

SMOD0

R,W

Baud Rate Double Bit (UART0)

0 = No doubling

1 = Doubling

(See Section 21.3: UART baud rates on page 110 for details.)

SMOD1

R,W

Baud Rate Double Bit for 2nd UART (UART1)

0 = No doubling

1 = Doubling

(See Section 21.3: UART baud rates on page 110 for details.)

–

Reserved

4POR

R,W

Only a power-on reset sets this bit (cold reset). Warm reset

will not set this bit.

0 = Cleared to zero with firmware

1 = Is set only by a power-on reset generated by Supervisory

circuit (see Section 19.3: Power-up reset on page 92 for

details).

RCLK1

R,W

Received Clock Flag (UART1)

(See Table 60 on page 101 for flag description.)

TCLK1

R,W

Transmit Clock Flag (UART1)

(See Table 60 on page 101 for flag description)

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