UPSD3422EB40U6 datasheet(66/300 Pages) STMICROELECTRONICS

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

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13.1.9

USB interrupt

The USB interrupt has multiple sources. The ISR must read the USB interrupt flag registers

(UIF0-3) to determine the source of the interrupt.

The USB interrupt can be activated by any of the following four group of interrupt sources:

●

Global: the interrupt flag is set when any of the following events occurs: USB Reset,

USB Suspend, USB Resume, and End of Packet;

●

In FIFO: the interrupt flag is set when any of the End Point In FIFO becomes empty;

●

Out FIFO: the interrupt flag is set when any of the End Point Out FIFO becomes full;

and

●

In FIFO NAK: the interrupt flag is set when any of the End Point In FIFO is not ready for

an IN (in-bound) packet.

Table 18.

IE: interrupt enable register (SFR A8h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

ET2

ES0

ET1

EX1

ET0

EX0

Table 19.

IE register bit definition

Bit

Symbol

R/W

Function

7EA

R,W

Global disable bit. 0 = All interrupts are disabled. 1 = Each

interrupt source can be individually enabled or disabled by

setting or clearing its enable bit.

6–

R,W

Do not modify this bit. It is used by the JTAG debugger for

instruction tracing. Always read the bit and write back the

same bit value when writing this SFR.

5(1)

1 = Enable Interrupt, 0 = Disable Interrupt.

ET2

R,W

Enable Timer 2 Interrupt

4(1)

ES0

R,W

Enable UART0 Interrupt

3(1)

ET1

R,W

Enable Timer 1 Interrupt

2(1)

EX1

R,W

Enable External Interrupt INT1

1(1)

ET0

R,W

Enable Timer 0 Interrupt

0(1)

EX0

R,W

Enable External Interrupt INT0

Table 20.

IEA: interrupt enable addition register (SFR A7h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EADC

ESPI

EPCA

ES1

–

EI2CEUSB

Table 21.

IEA register bit definition

Bit

Symbol

R/W

Function

7(1)

EADC

R,W

Enable ADC Interrupt

6(1)

ESPI

R,W

Enable SPI Interrupt

5(1)

EPCA

R,W

Enable Programmable Counter Array Interrupt

4(1)

ES1

R,W

Enable UART1 Interrupt

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